AD14060/AD14060L
16.0
14.0
12.0
10.0
8.0
(per data line). T he hold time will be tDECAY plus the minimum
disable time (i.e., tHDWD for the write cycle).
14.7
REFERENCE
SIGNAL
RISE TIME
tMEASURED
7.4
tENA
tDIS
FALL TIME
6.0
V
OH (MEASURED)
V
OH (MEASURED)
V
– ∆V
+ ∆V
2.0V
1.0V
OH (MEASURED)
4.0
3.7
V
OL (MEASURED)
V
V
OL (MEASURED)
OL (MEASURED)
2.0
1.1
tDECAY
0
0
20
40
60
80
100 120 140 160 180 200
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
LOAD CAPACITANCE – pF
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
Figure 30. Typical Output Rise Tim e (10%–90% VDD
vs. Load Capacitance (VDD = 5 V)
)
APPROXIMATELY 1.5V
Figure 27. Output Enable/Disable
3.5
3.0
I
OL
2.9
1.6
2.5
RISE TIME
2.0
TO
OUTPUT
PIN
+1.5V
1.5
50pF
FALL TIME
1.0
0.6
0.5
I
OH
0
0
20
40
60
80 100 120 140 160 180 200
Figure 28. Equivalent Device Loading for AC Measure-
m ents (Includes All Fixtures)
LOAD CAPACITANCE – pF
Figure 31. Typical Output Rise Tim e (0.8 V –2.0 V)
vs. Load Capacitance (VDD = 5 V)
INPUT OR
OUTPUT
1.5V
1.5V
Figure 29. Voltage Reference Levels for AC Measure-
m ents (Except Output Enable/Disable)
5
4
3
2
1
4.5
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). T he delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 30 and 31
show how output rise time varies with capacitance. Figure 32
graphically shows how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see the previous section Output Disable
T ime under T est Conditions.) T he graphs of Figures 30, 31 and
32 may not be linear outside the ranges shown.
NOMINAL
–0.7
–1
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
Figure 32. Typical Output Delay or Hold vs. Load
Capacitance (at Maxim um Case Tem perature) (VDD = 5 V)
REV. A
–38–
ADI [ ADI ]
