AD14060/AD14060L
Ser ial P or ts
P aram eter
5 V
3.3 V
Min
Max
Min
Max
Units
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
4
4.5
2
4.5
9.5
tCK
4
4.5
2
4.5
9
tCK
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
TCLK/RCLK Width
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
9
1
4
3
9
1
4
3
ns
ns
ns
ns
tHFSI
tSDRI
tHDRI
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
tHFSE
RFS Delay After RCLK (Internally Generated RFS)3
14
14
ns
ns
RFS Hold After RCLK (Internally Generated RFS)3
3
3
External Clock
Switching Characteristics:
tDFSE
tHFSE
tDDTE
tHDTE
TFS Delay After TCLK (Internally Generated TFS)3
14
17
14
17
ns
ns
ns
ns
TFS Hold After TCLK (Internally Generated TFS)3
Transmit Data Delay After TCLK3
3
5
3
5
Transmit Data Hold After TCLK3
Internal Clock
Switching Characteristics:
tDFSI
tHFSI
tDDTI
tHDTI
tSCLKIW
TFS Delay After TCLK (Internally Generated TFS)3
5
5
8
ns
ns
ns
ns
TFS Hold After TCLK (Internally Generated TFS)3
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
TCLK/RCLK Width
–1.5
0
–1.5
0
8
(SCLK/2) – 2
(SCLK/2) + 2
(SCLK/2) – 2.5 (SCLK/2) + 2.5 ns
Enable and Three-State
Switching Characteristics:
tDDTEN
tDDTTE
tDDTIN
tDDTTI
tDCLK
Data Enable from External TCLK3
3.5
0
4
0
ns
ns
ns
ns
ns
ns
Data Disable from External TCLK3
Data Enable from Internal TCLK3
Data Disable from Internal TCLK3
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
11.5
11.5
3
3
23 + 3DT/8
18
23 + 3DT/8
18
tDPTR
External Late Fram e Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 04
tDDTENFS Data Enable from late FS or MCE = 1, MFD = 04
13
13.8
ns
ns
3.0
3.5
T o determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOT ES
1Referenced to sample edge.
2RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. T FS hold after T CK for late external T FS is 0.5 ns minimum from drive edge.
3Referenced to drive edge.
4MCE = 1, T FS enable and T FS valid follow tDDT LFSE and tDDT ENFS
.
REV. A
–33–
ADI [ ADI ]
