AD14060/AD14060L
Link P or ts: 1 × CLK Speed O per ation
P aram eter
5 V
3.3 V
Min
Max
Min
Max
Units
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1 × Operation)
LCLK Width Low
3.5
3
tCK
6
3
3
tCK
6
5
ns
ns
ns
ns
ns
LCLK Width High
5
Switching Characteristics:
tDLAHC
tDLALC
tENDLK
tT DLK
LACK High Delay After CLKIN High
18 + DT /2
–3
5 + DT /2
29.5 + DT /2
13.5
18 + DT /2
–3
5 + DT /2
29.5 + DT /2
13.5
ns
ns
ns
ns
LACK Low Delay After LCLK High1
LACK Enable from CLKIN
LACK Disable from CLKIN
21 + DT /2
21 + DT /2
Tr ansm it
Timing Requirements:
tSLACH LACK Setup Before LCLK High
tHLACH LACK Hold After LCLK High
18
–7
20
–7
ns
ns
Switching Characteristics:
tDLCLK
LCLK Delay After CLKIN (1 × Operation)
16.5
3.5
17.5
3
ns
ns
ns
ns
ns
tDLDCH
tHLDCH
tLCLKT WL
tLCLKT WH
tDLACLK
tENDLK
tT DLK
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
–3
–3
(tCK/2) – 2
(tCK/2) – 2
(tCK/2) + 8.5
5 + DT /2
(tCK/2) + 2
(tCK/2) + 2
(3 × tCK/2) + 17.5 (tCK/2) + 8
5 + DT /2
(tCK/2) – 1
(tCK/2) + 1.25
(tCK/2) – 1.25 (tCK/2) + 1
LCLK Width High
LCLK Low Delay After LACK High
LDAT , LCLK Enable After CLKIN
LDAT , LCLK Disable After CLKIN
(3 × tCK/2) + 18 ns
ns
ns
21 + DT /2
21 + DT /2
Link P or t Ser vice Request Inter r upts:
1 × and 2 × Speed O per ations
Timing Requirements:
tSLCK
tHLCK
LACK/LCLK Setup Before CLKIN Low2
10
2.5
10
2.5
ns
ns
LACK/LCLK Hold After CLKIN Low2
NOT ES
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2Only required for interrupt recognition in the current cycle.
REV. A
–30–