AD14060/AD14060L
Link P or ts: 2 × CLK Speed O per ation
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
R
eceive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup Before LCLK Low
2.5
2.25
2.25
tCK/2
5
ns
ns
ns
ns
ns
Data Hold After LCLK Low
LCLK Period (2 × Operation)
LCLK Width Low
2.25
tCK/2
4.5
LCLK Width High
4.25
4
Switching Characteristics:
tDLAHC LACK High Delay After CLKIN High
tDLALC
LACK Low Delay After LCLK High1
18 + DT /2
6
29.5 + DT /2
16.5
18 + DT /2
6
30.5 + DT /2
18.5
ns
ns
Tr ansm it
Timing Requirements:
tSLACH LACK Setup Before LCLK High
tHLACH LACK Hold After LCLK High
19
–6.75
19
–6.5
ns
ns
Switching Characteristics:
tDLCLK
tDLDCH
tHLDCH
tLCLKT WL
tLCLKT WH
tDLACLK
LCLK Delay After CLKIN
9
3
9
2.75
ns
ns
ns
ns
ns
ns
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
–2
–2
(tCK/4) – 1
(tCK/4) – 1
(tCK/4) + 9
(tCK/4) + 1
(tCK/4) + 1
(3 × tCL/4) + 17
(tCK/4) – 0.75 (tCK/4) + 1.5
(tCK/4) – 1.5
(tCK/4) + 9
(tCK/4) + 1
(3 × tCL/4) + 17
NOT E
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
REV. A
–31–
ADI [ ADI ]
