®
ACT8938
Rev 3, 23-Dec-11
user presses the push-button again. Asserting
nPBIN enables REG2, REG3, REG4 and REG5.
Once REG2 reaches regulation, REG3 is enabled
and the nRSTO timer begins. Once the reset timer
period expires the nRSTO output is de-
asserted and the processor initiates a boot-up
sequence, during which it should determine the
system status by reading the HBRDY[ ] bit; if the
value of HBRDY[ ] is 0 then the software should
proceed with a typical enable sequence, whereas if
the value of HBRDY[ ] is 1 then the software should
proceed with a “wake from Hibernate Mode”
routine. To complete the wake process, the
processor should assert PWRHLD, holding REG1,
and de-assert nHIB to logic high, holding REG2,
REG3, REG4 and REG5 to ensure that the system
remains enabled after the push-button is released
then set FRC_ON1[ ] and HBRDY[ ] to 0 to
complete a full wake-up routine.
Disable Sequence
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally de-assert PWRHLD and assert nHIB
to logic low, disabling all regulators and shutting the
system down. It is important that FRC_ON1[ ] is
clear to 0 prior to shutting down the system,
otherwise REG1 will remain ON.
Figure 3:
Enable Sequence
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