®
ACT8938
Rev 3, 23-Dec-11
Table 4:
ACT8938 Signal Interface with Marvell Aspen
ACT8938
SCL
DIRECTION
MARVELL ASPEN
PWR_SCL
SDA
PWR_SDA
VSEL
DVS_GPIOꢀ
RESET_IN_N
EXT_WAKEUPꢁ
EXT_WAKEUPꢂ
GPIOꢃ
nRSTO
nIRQ
nPBSTAT
PWRHLD
nHIB
GPIOꢄ
1: Optional connection for DVS control.
2, ꢂ: External wake up/interrupt signal used to wake up the processor from system idle mode.
ꢃ, ꢄ: Optional connection for shut down control.
Table 5:
Control Pins
PIN NAME
OUTPUT
nPBIN
PWRHLD
nHIB
REG1, REG2, REG3, REG4, REG5
REG1
REG2, REG3, REG4, REG5
Manual Reset Function
Control Signals
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
When this occurs, nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
Enable Inputs
The ACT8938 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
nHIB, PWRHLD are logic inputs, while nPBIN is a
unique, multi-function input. Refer to Table 5 for a
description of which channels are controlled by
each input.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT2) through a 10kꢀ or greater resistor.
nPBIN Multi-Function Input
ACT8938 features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50kꢀ resistor
to GA, as shown in Figure 2.
Figure 2:
nRSTO Output
nPBIN Input
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT2 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
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