®
ACT8938
Rev 3, 23-Dec-11
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT2).
reaches its power-OK threshold, REG4 is enabled
and nRSTO is asserted low, resetting the
microprocessor. REG3 is enabled when REG2
reaches its power-OK threshold for 2msꢀ. REG1 is
enabled when REG2 reaches its power-OK
threshold for 4msꢀ. REG5 is enabled when REG2
reaches its power-OK threshold for 8msꢀ. If REG2
is above its power-OK threshold when the reset
timer expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
During the boot sequence, the processor should
read the HBRDY[ ] bit; if the value of HBRDY[ ] is 0
then the software should proceed with a typical
enable sequence, whereas if the value of HBRDY[ ]
is 1 then the software should proceed with a “wake
from Hibernate Mode” routine. See the Hibernate
Mode Sequence section for more information.
During the boot sequence, the microprocessor must
assert PWRHLD, holding REG1, and set nHIB to a
logic high, holding REG2, REG3, REG4 and REG5
to ensure that the system remains powered after
nPBIN is released. REG6 and REG7 should be
enabled/disabled via I2C after microprocessor
completes its boot sequence.
Many of the ACT8938's functions support interrupt-
generation as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as PWRHLD is asserted and nHIB
is de-asserted. If the processor does not assert
PWRHLD or de-assert nHIB to logic high before the
user releases the push-button, the boot-up
sequence is terminated and all regulators are
disabled. This provides protection against "false-
enable", when the push-button is accidentally
depressed, and also ensures that the system
remains enabled only if the processor successfully
completes the boot-up sequence.
Push-Button Control
The ACT8938 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWRHLD and de-asserting nHIB) before nPBIN is
de-asserted. If the microprocessor is unable to
complete its power-up routine successfully before
the user releases the push-button, the ACT8938
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
asserting PWRHLD and de-asserting nHIB.
Hibernate Mode Sequence
The ACT8938 supports Hibernate mode of
operation for Aspen processor. Once a successful
power-up routine is completed, Hibernate mode
may be initiated through a variety of software-
controlled mechanisms. Hibernate mode is typically
initiated when the user presses the push-button
during normal operation. Pressing the push-button
asserts the nPBIN input, which asserts the
nPBSTAT output to interrupt the processor. In
response to this interrupt the processor should first
set the FRC_ON1[ ] bit to 1, and the HBRDY[ ] bit to
1. Then the processor should assert nHIB to logic
low, disabling REG2, REG3, REG4, REG5.
Control Sequences
The ACT8938 features
sequences that are optimized for supporting system
enable and disable, as well as Hibernate mode of
the Aspen processors.
a
variety of control
Enable Sequence
A typical enable sequence initiates as a result of
asserting nPBIN, and begins by enabling REG2,
REG4, REG3, REG1 and REG5. When REG2
Waking from Hibernate mode is initiated when the
ꢀ: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
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