ACT88430QJ-T
Rev 1.0, 24-Oct-2018
3. Place the LDO input capacitors close to their input
pins. Connect their ground pins into the ground
plane that connects the IC’s exposed pad.
Output Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
output capacitor. A 1uF is typically suitable, but this
value can be increased without limit. The input capacitor
is should be a X5R, X7R, or similar dielectric.
4. The input capacitor and output capacitor grounds
should be connected as close together as possible,
with short, direct, and wide traces.
LDO1 Load Switch Mode
LDO1 has an option to be used as a load switch. This
option is only accessible via factory I2C bits and requires
a custom CMI. When in load switch mode, LDO1 still
retains overcurrent protection. Overvoltage and
undervoltage protection are disabled.
5. Connect the PGNDx ground pins and the AGND
ground pin directly to the exposed pad under the IC.
The AGND ground plane should be routed
separately from the other ground planes and only
connect to the main ground plane under the IC at
the AGND pin.
The load switch mode softstart times are the same as
the LDO mode times.
6. Connect the VIO_IN input capacitor to the AGND
ground pin.
The following table shows the load switch Current limit
settings
7. Connect the VIN input capacitor to the AGND
ground pin.
Table 7: Load Switch Current Limit Settings
8. Remember that all open drain outputs need pullup
resistors.
ILIM_SET<1:0>
ILIM(mA)
1415
1503
1626
1904
0
1
2
3
9. Connect the exposed pad directly the top layer
ground plane. Connect the top layer ground plane
to both internal ground planes and the PCB
backside ground plane with thermal vias. Provide
ground plane routing on multiple layers that allows
the IC’s heat to flow into the PCB and then spread
radially from the IC. Avoid cutting the ground planes
and adding vias that restrict the radial flow of heat
of operating conditions, and are relatively
insensitive to layout considerations.
Both Overvoltage and Undervoltage functionality are
disabled.
The LDO1 POK is functional in Load Switch mode. The
POK signal is asserted when the switch is enabled and
is not in current limit.
PC board layout guidance
Proper parts placement and PCB layout are critical to
the operation of switching power supplies. Follow the
following layout guidelines when designing the
ACT88430 PCB. Refer to the Active-Semi ACT88430
Evaluation Kits for layout examples
1. Place the buck input capacitors as close as possible
to the IC. Connect the capacitors directly to the
corresponding VIN_Bx input pin and PGNDx power
ground pin. Avoid the use of vias if possible.
2. Minimize the switch node trace length between
each SW_Bx pin and the inductor. Avoid routing
sensitive analog signals near these high frequency,
high dV/dt traces.
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