ACT81460
Rev 1.0, 18-Dec-2018
output current which causes the output voltage to drop.
When LDOx_ILIM_SHUTDOWN_DIS = 1, the LDO
turns off when it reaches current limit. When the register
= 0, and the UV fault is masked, the output voltage
drops based on the load resistance. When the output
voltage drops below 1V, the current folds back to
~60mA to reduce power dissipation in the IC. If the UV
fault is not masked, the LDO shuts off when the output
voltage drops below the UV threshold, waits 100ms,
and then tries to restart.
Output Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
output capacitor. A 2.2uF capacitor to AGND is typically
suitable, but this value can be increased without limit.
The output capacitor is should be a X5R, X7R, or similar
dielectric. The LDO effective output capacitance must
be greater than 0.8uF.
LDO3 in Load Switch Mode
LDO3 can be configured as a load switch. Configure
LDO3 into LDO mode by setting I2C bit
EN_LDOx_LOAD_SWITCH_MODE = 0. Configure it
into load switch mode by setting the register = 1.
The LDO’s real-time current limit status is reported in
the ILIM_LDOx I2C registers. The contents of these reg-
isters are latched until read via I2C. When in current limit,
the IC asserts nIRQ low provided the fault is not masked.
Overcurrent and short circuit conditions can be masked
via the I2C bit ILIM_FLTMSK_LDOx. When masked, the
LDO still shuts down or limits current (based on the
LDOx_ILIM_SHUTDOWN_DIS bit). If the IC shuts down
due to current limit, it automatically restarts in 14ms.
When LDO3 reaches current limit, the output turns off
for 14ms and then restarts. It continues in the “hiccup”
mode until the overcurrent condition is removed. LDO3
does not generate an interrupt in an overcurrent condi-
tion.
Note that LSW456 do generate an interrupt with an
overcurrent condition.
Compensation
The LDOs are internally compensated and require very
little design effort, simply select input and output capac-
itors according to the guidelines below.
Input Capacitor Selection
Each LDO has a dedicated input pin, VINL1, VINL2, and
VINL3. Each input pin requires a high quality, low-ESR,
ceramic input capacitor. A 1uF capacitor to AGND is
typically suitable, but this value can be increased
without limit. The input capacitor should be a X5R, X7R,
or similar dielectric.
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