PLUS
ProASIC
Flash Family FPGAs
÷1
÷n
Global MUX B OUT
270
180
˚
˚
GLB
D
133 MHz
PLL Core
÷u
÷1
90
133 MHz
˚
÷m
÷1
0
˚
D
D
External Feedback
Global MUX A OUT
÷v
D
GLA
Figure 1-18 • Using the PLL to Delay the Input Clock
÷1
Global MUX B OUT
133 MHz
÷n
270
˚
GLB
D
180
˚
PLL Core
÷u
÷1
133 MHz
90
˚
÷m
÷1
0
˚
D
D
External Feedback
Global MUX A OUT
÷v
D
GLA
Figure 1-19 • Using the PLL to Advance the Input Clock
1-18
v5.2