Actel Fusion Mixed-Signal FPGAs
CCC
CCC
CCC
Bank 0
Bank 1
Up to five VREF
minibanks within
an I/O bank
Common VREF
signal for all I/Os
in VREF minibanks
VREF signal scope is
between 8 and 18 I/Os.
If needed, the VREF for a given
minibank can be provided by
any I/O within the minibank.
I/O Pad
Figure 2-91 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side of AFS600 and AFS1500)
Table 2-64 • I/O Standards Supported by Bank Type
Differential I/O
Hot-
I/O Bank
Single-Ended I/O Standards
Standards
Voltage-Referenced
Swap
Standard I/O LVTTL/LVCMOS 3.3 V, LVCMOS –
2.5 V / 1.8 V / 1.5 V, LVCMOS
2.5/5.0 V
–
–
Yes
Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL and LVDS
2.5 V / 1.8 V / 1.5 V, LVCMOS
–
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X
Pro I/O
LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL and LVDS GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, Yes
2.5 V / 1.8 V / 1.5 V, LVCMOS
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X
HSTL Class I and II, SSTL2 Class I and
II, SSTL3 Class I and II
Preliminary v1.7
2-131
ACTEL [ Actel Corporation ]
