Actel Fusion Mixed-Signal FPGAs
CCC and PLL Characteristics
Timing Characteristics
Table 2-13 • Fusion CCC/PLL Specification
Parameter
Min.
1.5
Typ.
Max.
350
Unit
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks1, 2
0.75
350
160
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
1.00%
1.50%
2.25%
3.50%
1.00%
1.50%
2.25%
3.50%
300
Acquisition Time
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
µs
ms
ns
ns
%
ns
ns
ns
6.0
Tracking Jitter3
1.6
0.8
Output Duty Cycle
48.5
0.6
51.5
5.56
5.56
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
2.2
1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-9 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
Preliminary v1.7
2-31
ACTEL [ Actel Corporation ]
