Device Architecture
Real-Time Counter System
The addition of the RTC system enables Fusion devices to support both standby and sleep modes of
operation, greatly reducing power consumption in many applications.
The RTC system comprises six blocks that work together to provide this increased functionality and
reduced power consumption. Figure 2-27 shows these blocks and how they are connected.
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RTC (Figure 2-28)
Crystal oscillator
VCC33UP detector
Voltage regulator initialization
Voltage regulator logic
1.5 V voltage regulator
The RTC provides a counter as well as a MATCH output signal that can be used in the FPGA and,
optionally, to power up the on-chip 1.5 V voltage regulator and provide a 1.5 V power source (in
conjunction with an external pass transistor) to the FPGA fabric portion of the Fusion silicon device.
The FPGA fabric can then be used to power down the 1.5 V voltage regulator.
1.5 V FPGA Supply Input
FPGA Fabric
1.5/3.3 Volt Level Shift Circuitry
3.3 V
From
Core Flash
Bits
RTC
VR Logic
Crystal Oscillator
1.5 V Voltage
Regulator
MODE[1:0]
VR Init
Flash Bits
ACM
External
Pass
Transistor
0
RTCMATCH
PTBASE
FPGA_VRON
VRFPD
RTCMODE[1:0]
VRINITSTATE
EN
SELMODE
XTAL1
XTAL2
PTEM
PUB
RTCPSMMATCH
VRON
RTCPSMMATCH
1.5 V
Output
VRPU
CLKOUT
RTCCLK
VCC33UP
~ VRPSM
Power-Up/Down
Toggle Control
Switch
Figure 2-27 • Real-Time Counter System
2-34
Preliminary v1.7
ACTEL [ Actel Corporation ]
