Actel Fusion Mixed-Signal FPGAs
CCC Physical Implementation
The CCC circuit is composed of the following (Figure 2-23):
•
•
•
•
PLL core
3 phase selectors
6 programmable delays and 1 fixed delay
5 programmable frequency dividers that provide frequency multiplication/division (not
shown in Figure 2-23 because they are automatically configured based on the user's
required frequencies)
•
1 dynamic shift register that provides CCC dynamic reconfiguration capability (not shown)
CCC Programming
The CCC block is fully configurable. It is configured via static flash configuration bits in the array,
set by the user in the programming bitstream, or configured through an asynchronous dedicated
shift register, dynamically accessible from inside the Fusion device. The dedicated shift register
permits changes of parameters such as PLL divide ratios and delays during device operation. This
latter mode allows the user to dynamically reconfigure the PLL without the need for core
programming. The register file is accessed through a simple serial interface.
CLKA
Four-Phase Output
GLA
Programmable
Delay Type 2
Phase
Select
PLL Core
Programmable
Delay Type 1
Fixed Delay
Programmable
Delay Type 2
GLB
YB
Phase
Select
Programmable
Delay Type 1
Programmable
Delay Type 2
GLC
Phase
Select
YC
Programmable
Delay Type 1
Note: Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are automatically
configured based on the user's required frequencies.
Figure 2-23 • PLL Block
Preliminary v1.7
2-29
ACTEL [ Actel Corporation ]
