Actel Fusion Mixed-Signal FPGAs
Global Buffers with Programmable Delay
The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability
to delay the clock input using a programmable delay (Figure 2-21). The CLKDLY macro takes the
selected clock input and adds a user-defined delay element. This macro generates an output clock
phase shift from the input clock.
The CLKDLY macro can be driven by an INBUF macro to create a composite macro, where the I/O
macro drives the global buffer (with programmable delay) using a hardwired connection. In this
case, the I/O must be placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of single-ended and differential I/O standards
supported by the Fusion family. The available INBUF macros are described in the Fusion, IGLOO/e
and ProASIC3/E Macro Library Guide.
The CLKDLY macro can be driven directly from the FPGA core.
The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the
hardwired I/O connection described earlier.
The visual CLKDLY configuration in the SmartGen part of the Libero IDE and Designer tools allows
the user to select the desired amount of delay and configures the delay elements appropriately.
SmartGen also allows the user to select the input clock source. SmartGen will automatically
instantiate the special macro, PLLINT, when needed.
Clock Source
Clock Conditioning
Output
GLA
or
Input LVDS/LVPECL Macro
CLK
GL
PADN
PADP
Y
GLB
or
DLYGL[4:0]
GLC
INBUF* Macro
Y
PAD
Figure 2-21 • Fusion CCC Options: Global Buffers with Programmable Delay
Preliminary v1.7
2-27
ACTEL [ Actel Corporation ]
