Actel Fusion Mixed-Signal FPGAs
Analog Configuration MUX (ACM) Interface
Control/Status
Register
Main
Registers
40-Bit
Read-Hold
Register
7-Bit Prescaler
(Crystal ÷ 128)
40-Bit
Counter
40-Bit Match
Register
Match
Bits
40 XNORs
Match
Figure 2-28 • RTC Block Diagram
Real-Time Counter
The RTC can be configured to power up the FPGA fabric at a specific time or periodically. Custom
user logic or a soft microcontroller within the FPGA fabric portion of the Fusion device can be
programmed to read and modify the registers in the RTC. Based on this information or other
internal or external conditions, the FPGA may decide to power down the voltage regulator and
thereby shut off the FPGA fabric.
The 3.3 V supply must be valid and the crystal oscillator (nominally 32.768 kHz) enabled for a self-
timed wake-up/restart operation. When operating from the 3.3 V supply with the 1.5 V core
voltage disabled, the ACM interface to the FPGA is disabled.
A 40-bit loadable counter is used as the primary timekeeping element within the RTC. This counter
can be configured to reset itself when a count value is reached that matches the value set within a
40-bit match register. Note that the only exception to this self-clearing mechanism occurs when the
40-bit counter is equal to zero (0x0000000000), since the counter would never increment from
zero. When the device is first powered up (i.e., when the 3.3 V supply becomes valid), the 40-bit
counter and 40-bit match register are cleared to logic 0, and the MATCH output signal is active
(logic 1). At any time when the 40-bit counter value does not match the value in the 40-bit match
register, the MATCH output signal will become inactive (logic 0).
Both the counter and match registers are addressable (read/write) from the FPGA and through a
JTAG instruction. The RTC is considered part of the analog system and is accessed via the ACM.
Refer to the "Analog Configuration MUX" section on page 2-124 for detailed instructions on
writing to the RTC via the ACM. The counter action can be suspended/resumed by clearing/setting
the Cntr_En bit in the Control/Status register.
If a 32.768 kHz external crystal is connected to the crystal oscillator pad, the 40-bit counter will
have a maximum count of 4,294,967,296 seconds, which equates to just over 136 years of elapsed
timekeeping with a minimum period of 1/256 of a second, which will be the toggle rate of the LSB
of the 40-bit counter.
Frequencies other than 32.768 kHz can be used as a clock source with the appropriate scaling of
the LSB time interval. The maximum input clock frequency is 20 MHz (the crystal oscillator limit).
The RTC signals are included in the Analog Block macro. The signal functions and descriptions are
listed in Table 2-15.
A Fusion use model includes the RTC controlling the power-up state of the FPGA core via the 1.5 V
regulator. To support this model, the crystal oscillator must be running and configured when the
FPGA is powered off. Hence, when the RTC is enabled in the system design, it will configure the
crystal oscillator via the RTCXTLMODE[1:0] and RTCXTLSEL pins.
A 7-bit prescaler block is used to divide the source clock (from the external crystal) by 128. This
prescaled 50%-duty-cycle clock signal is then used by the counter logic as its reference clock. Given
Preliminary v1.7
2-35
ACTEL [ Actel Corporation ]
