Device Architecture
Clock Conditioning Circuits
In Fusion devices, the CCCs are used to implement frequency division, frequency multiplication,
phase shifting, and delay operations.
The CCCs are available in six chip locations—each of the four chip corners and the middle of the
east and west chip sides.
Each CCC can implement up to three independent global buffers (with or without programmable
delay), or a PLL function (programmable frequency division/multiplication, phase shift, and delays)
with up to three global outputs. Unused global outputs of a PLL can be used to implement
independent global buffers, up to a maximum of three global outputs for a given CCC.
A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC-
GLC) of a given CCC.
A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and, optionally,
the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB
and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC)
output is used (Figure 2-19). Refer to the "PLL Macro" section on page 2-30 for more information.
Each global buffer, as well as the PLL reference clock, can be driven from one of the following:
•
•
•
3 dedicated single-ended I/Os using a hardwired connection
2 dedicated differential I/Os using a hardwired connection
The FPGA core
The CCC block is fully configurable, either via flash configuration bits set in the programming
bitstream or through an asynchronous interface. This asynchronous interface is dynamically
accessible from inside the Fusion device to permit changes of parameters (such as divide ratios)
during device operation. To increase the versatility and flexibility of the clock conditioning system,
the CCC configuration is determined either by the user during the design process, with
configuration data being stored in flash memory as part of the device programming procedure, or
by writing data into a dedicated shift register during normal device operation. This latter mode
allows the user to dynamically reconfigure the CCC without the need for core programming. The
shift register is accessed through a simple serial interface. Refer to the UJTAG Applications in Actel’s
Low-Power Flash Devices handbook chapter and the "CCC and PLL Characteristics" section on
page 2-31 for more information.
2-24
Preliminary v1.7
ACTEL [ Actel Corporation ]
