Actel Fusion Mixed-Signal FPGAs
Clock Source
Clock Conditioning
Output
CLKA
GLA
LOCK
Input LVDS/LVPECL Macro
EXTFB
POWERDOWN
GLA
or
GLB
YB
GLC
YC
PADN
PADP
Y
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
OADIVRST
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
INBUF2 Macro
Y
PAD
XDLYSEL
VCOSEL[2:0]
Notes:
1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. Refer to the
"PLL Macro" section on page 2-30 for signal descriptions.
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the
Fusion family.
3. Refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide for more information.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
Table 2-12 • Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS331
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKBUF_LVDS2
CLKBUF_LVPECL
Notes:
1. This is the default macro. For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library
Guide.
2. The BLVDS and M-LVDS standards are supported with CLKBUF_LVDS.
Preliminary v1.7
2-25
ACTEL [ Actel Corporation ]
