HiRel FPGAs
A14100A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=256)
9.0
9.0
10.5
10.5
ns
ns
Input High to Low (FO=256)
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
Maximum Skew (FO=128)
6.3
6.3
7.1
7.1
ns
ns
1.9
75
2.1
65
ns
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.5
5.0
0.0
0.0
3.5
5.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
47
ACTEL [ Actel Corporation ]
