A32100DX Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
Internal Decode Module Delay
3.1
3.3
4.1
4.3
ns
ns
tPDD
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.3
1.9
2.6
3.3
0.6
0.5
1.8
2.6
3.4
4.3
0.8
0.6
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
3.1
3.1
4.1
4.1
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSU
Flip-Flop (Latch) Setup Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.5
0.0
0.6
0.0
tH
tRO
3.1
4.1
tSUENA
tHENA
tWCLKA
0.9
0.0
1.2
0.0
Flip-Flop (Latch) Clock Active Pulse
Width
4.3
5.6
5.8
7.5
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
48
ACTEL [ Actel Corporation ]
