HiRel FPGAs
A14100A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.2
1.2
0.6
2.4
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Setup
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Setup
(w.r.t. IOCLK Pad)
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
8.9
14.0
7.0
ns
ns
tDLS
Data to Pad, Low Slew
11.9
6.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
11.9
10.9
12.2
17.8
0.04
0.07
0.05
0.07
12.8
14.0
12.8
14.0
17.8
0.04
0.08
0.06
0.08
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35 pF loading.
45
ACTEL [ Actel Corporation ]
