HiRel FPGAs
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
5.1
6.3
6.8
8.3
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.4
ns
Enable Pad High to Z
11.5
11.5
11.5
12.4
15.3
15.3
15.3
16.6
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Output Setup
I/O Latch Output Hold
0.4
0.0
0.5
0.0
ns
tLH
ns
tLCO
tACO
dTLH
dTHL
tWDO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
11.5
16.3
0.04
0.06
0.05
15.4
21.7
0.06
0.08
0.07
ns
ns
ns/pF
ns/pF
ns
CMOS Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
6.3
5.1
8.3
6.8
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.4
ns
Enable Pad High to Z
11.5
11.5
11.5
12.4
15.3
15.3
15.3
16.6
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Setup
0.4
0.0
0.5
0.0
ns
tLH
I/O Latch Hold
ns
tLCO
tACO
dTLH
dTHL
tWDO
Notes:
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
13.7
19.2
0.06
0.05
0.05
18.2
25.6
0.08
0.07
0.07
ns
ns
ns/pF
ns/pF
ns
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
51
ACTEL [ Actel Corporation ]
