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5962-9958502QXC 参数 Datasheet PDF下载

5962-9958502QXC图片预览
型号: 5962-9958502QXC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 36000 Gates, 2414-Cell, CMOS, CQFP256, CERAMIC, QFP-256]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX J  
J.3.4 Constant acceleration. All microcircuits shall be subjected to constant acceleration, except as modified in  
accordance with 4.2 in the Y1 axis only, in accordance with TM 2001 of MIL-STD-883, condition E (minimum).  
Microcircuits which are contained in packages that have an inner seal or cavity perimeter of two inches or more in  
total length, or have a package mass of five grams or more, may be tested by replacing condition E with condition D  
in TM 2001 of MIL-STD-883. For packages that cannot tolerate the stress level of condition D, the manufacturer shall  
have data to justify a reduction in the stress level. The reduced stress level shall be specified in the manufacturers  
QM plan. The minimum stress level allowed in this case is condition A.  
J.3.5 Burn-in. Burn-in shall be performed on all QML microcircuits, except as modified in accordance with section  
4.2, at or above their maximum rated operating temperature (for devices to be delivered as wafer or die, burn-in of  
packaged samples from the lot shall be performed to a quantity accept level of 10(0)). For microcircuits whose  
maximum operating temperature is stated in terms of ambient temperature (TA), table I of TM 1015 of MIL-STD-883  
applies. For microcircuits whose maximum operating temperature is stated in terms of case temperature (TC), and  
where the ambient temperature would cause TJ to exceed +175°C, the ambient operating temperature may be  
reduced during burn-in from +125°C to a value that will demonstrate a TJ between +175°C and +200°C and TC equal  
to or greater than +125°C without changing the test duration. Data supporting this reduction shall be available to the  
acquiring and qualifying activities upon request.  
J.3.6 Final electrical measurements. Final electrical testing of microcircuits shall assure that the microcircuits  
tested meet the electrical requirements of the device specification and shall include the tests of table III, group A,  
subgroups 1, 2, 3, 4 or 7, 5 and 6 or 8, and 9, 10, and 11, unless otherwise specified in the device specification.  
J.3.7 Seal (fine and gross leak) testing. Fine and gross leak seal tests shall be performed, as specified in 4.2,  
between temperature cycling and final electrical testing after all shearing and forming operations on the terminals in  
accordance with TM 1014 of MIL-STD-883.  
J.3.8 Pattern failures. Pattern failure criteria may be used as an option for any screen provided that pre burn-in  
testing is done. When acceptance is based on pattern failures (multiple device failures - two or more caused by the  
same basic failure mechanism) shall apply as specified in the acquisition document. If not otherwise specified, the  
maximum allowable failures shall be five devices for each failure pattern established. Accountability shall include  
burn-in through final electrical test.  
J.3.8.1 Pattern failure rejects. When the number of pattern failures exceeds the specified limits, the burn-in lot  
shall be rejected. At the manufacturer's TRB option, the rejected lot may be resubmitted to burn-in one time  
provided:  
a. The cause of the failure has been determined and evaluated.  
b. Appropriate and effective corrective action has been completed to reject all microcircuits affected by the  
failure cause.  
c. Appropriate preventive action has been initiated.  
J.3.9 TCI. TCI testing shall be accomplished by the manufacturer on a periodic basis to assure that the  
manufacturer's quality, reliability, and performance capabilities meet the requirements of the QM plan. The  
manufacturer of QML microcircuits shall be certified by the qualifying activity to use one or a combination of both of  
the TCI procedures described below. The two TCI procedures are end-of-line TCI (option 1, see J.3.10) and in-line  
TCI testing (option 2, see J.3.11).  
NOTE: All tests may not be appropriate for the technology (e.g., for wafer or die product, group B, subgroups 1  
and 3 and group D do not apply). The manufacturer's TRB shall determine that the appropriate tests are  
completed to assure conformance of the product to be delivered.  
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