MIL-PRF-38535K
APPENDIX H
H.3.4.4.1 Package integrity demonstration test plan (PIDTP) . Manufacturability, test, quality and reliability issues unique to
specific non-traditional assembly/package technologies intended for space applications shall be addressed in a Package
Integrity Demonstration Test Plan at the start of the package design cycle. The PIDTP shall be approved by QA after
consultation with the space community. The technologies requiring such a plan are: a) non-hermetic packages (e.g., class Y),
b) flip-chip assembly, and c) solder terminations. Microcircuits employing more than one of these technologies shall include
elements for each in the PIDTP.
H.3.4.4.1.1 Non-Hermetic packages. For class Y microcircuits, the PIDTP must address issues unique to non-hermetic
construction and materials, such as potential materials degradation, moisture absorption, and resistance of active devices,
passive devices and interconnects to environmental effects and processing stresses. Moisture sensitivity level characterization
(ref: IPC/JEDEC J-STD-020D) shall be performed for exposed flip-chip underfill or thermal grease/epoxy.
H.3.4.4.1.2 Flip-chip assembly. For space microcircuits employing flip-chip assembly technologies either class V or class Y
(class level S), the PIDTP must address the materials and processes unique to solder bump interconnect attach, underfill and
lid-to-die attach. The plan shall demonstrate as a minimum, how the following are evaluated and monitored including a
corresponding package level reliability demonstration:
1) Substrate materials. The substrate materials shall be documented in the PIDTP, and shall include landing pad
composition.
2) Bump geometry. The solder bump geometry shall be documented in the PIDTP, and shall include bump height, bump
diameter and bump pitch, as well as a description of the under bump metallurgy (UBM) shape, size and thickness.
3) Solder bump deposition process and materials. The solder bump deposition process shall be documented in the
PIDTP (e.g., plated, evaporation, solder paste), along with the solder alloy. In addition, the UBM deposition process (e.g.,
plated, evaporation, sputtered) and composition shall be documented in the PIDTP.
4) Flux materials. The flux type (e.g., no-clean, water soluble) and materials employed for solder bump interconnect
reflow shall be documented in the PIDTP.
5) Underfill materials. Underfill materials shall be documented in the PIDTP. All underfill materials shall meet MIL-STD-
883 TM 5011 requirements and outgassing requirement shall meet ASTM E595 test method.
6) Lid attach/adhesive materials. If a lid or heat spreader is attached to the back of a microcircuit die, the lid
attach/adhesive materials shall be documented in the PIDTP. All lid attach/adhesive materials shall meet the requirements of
TM 5011, MIL-STD-883, and outgassing requirements shall meet the test method ASTM E595.
7) Flip chip bump shear test. For flip chip, a bump shear test shall be performed in accordance with JEDEC JESD22-
B117 or equivalent to determine the shear strength of the solder bumps for initial qualification as a part of the wafer bump
technology qualification and shall be documented to the PIDTP.
H.3.4.4.1.3 Solder terminations. For space use microcircuits employing solder terminations (class V or class Y), the PIDTP
shall address the materials and processes unique to solder terminations, such as ball/column integrity, attachment integrity,
damage due to test, protection for shipment and shelf life. The manufacturer shall perform post column attachment electrical
characterization over temperature and compare data with pre-column attachment process to assess any changes due to the
column attachment process.
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ACTEL [ Actel Corporation ]
