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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX A  
A.3.5.4.3 Die to terminal interconnection. There shall be an enlarged photograph(s), transparency, or drawing(s)  
to scale and of sufficient magnification to clearly depict the interconnection pattern for all connections made by wire or  
ribbon bonding, beam leads or other methods between the semiconductor die, other elements of the microcircuit,  
substrate(s) and package terminals or lands as applicable to the specific type of microcircuit supplied. If these  
interconnections show clearly on the die intraconnection pattern photograph, an additional photograph or drawing is  
not required.  
A.3.5.4.4 Schematic diagrams. For microcircuits supplied under this appendix, the actual schematic diagram(s),  
logic diagram(s), or combination thereof shall be maintained, sufficient to represent all electrical elements functionally  
designed into the microcircuit together with their values (when applicable). For simple devices, this shall be a  
complete detailed schematic circuit showing all functional elements and values. For complex devices, or those with  
redundant detail, the overall microcircuit may be represented by a logic diagram in combination with schematic  
details. Minimum details that shall be included are: A schematic presentation of input/output stages and protection  
network details identified by appropriate pin numbers. Sufficient details to depict addressing or other device elements  
where the test parameters, conditions, or limits are sensitive to the specific device schematics. Where parasitic  
elements are important to the proper functioning of any microcircuit, they shall be included in the schematic diagram.  
A.3.5.5 Internal conductors. Internal thin film conductors on semiconductor die or substrate (metallization stripes,  
contact areas, bonding interfaces, etc.) shall be designed so that properly fabricated conductors shall not experience  
in normal operation, over the operating temperature range (see A.3.1.3.31) (at worst case specified operating  
conditions), a current density in excess of the maximum allowable value shown below for the applicable conductor  
material:  
Maximum allowable current  
Conductor material  
density  
Aluminum (99.99 percent pure or doped) without glassivation or without  
glassivation layer integrity test  
2 X 105 A/cm2  
Aluminum (99.99 percent pure or doped) glassivated (see A.3.5.5.4)  
5 X 105 A/cm2  
5 X 105 A/cm2  
6 X 105 A/cm2  
1 X 106 A/cm2  
2 X 105 A/cm2  
Refractory metals (Mo, W, Ti-W, and Ti-N) glassivated (see A.3.5.5.4)  
Gold  
Copper  
All other  
The current density shall be calculated at the point(s) of maximum current density (e.g., greatest current (see  
A.3.5.5a) in accordance with unit cross section) for the specific device type and schematic or configuration. Individual  
device calculations are not required when appropriate documented design rules or requirements have been used,  
which limit or control the current density in the resulting design.  
a. Use a current value equal to the maximum continuous current (at full fan-out for digitals or at maximum load  
for linear) or equal to the simple time averaged current obtained at maximum rated frequency and duty  
cycle with maximum load, whichever results in the greater current value at the point(s) of maximum current  
density. This current value shall be determined at the maximum recommended supply voltage(s) and with  
the current assumed to be uniform over the entire conductor cross-sectional area.  
b. Use the minimum allowed metal thickness in accordance with manufacturing specifications and controls  
including appropriate allowance for thinning experienced in the metallization step. The thinning factor over  
a metallization step is not required unless the point of maximum current density is located at the step.  
c. Use the minimum actual design conductor widths (not mask widths) including appropriate allowance for  
narrowing or undercutting experienced in metal etching.  
d. Areas of barrier metals, not intended by design to contribute to current carrying capacity, and non-  
conducting material shall not be included in the calculation of conductor cross section.  
Thick film conductors multichip substrates (metallization strips, bonding interfaces, etc.) shall be designated so that  
no properly fabricated conductor shall dissipate more than 4 watts/cm2 when carrying maximum design current.  
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