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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX H  
H.3.2.1.3.2 Parametric monitor (PM) . The manufacturer should have PMs to be used for measuring electrical  
characteristics of each wafer type in a specified technology. The PM test structures can be incorporated into the grid (kerf),  
within a device chip, as a dedicated drop-in die or any combination thereof. Location of the PM test structures should be  
optimally positioned to allow for the determination of the uniformity across the wafer. A suggested location scheme is one near  
the wafer center and one in each of the four quadrants of the wafer, at least two-thirds of a radius away from the wafer center.  
The manufacturer should establish, and document, reject limits and procedures for parametric measurements including which  
parameters shall be monitored routinely and which shall be included in the SPC program. Documentation of the PM should  
also include PM test structure design, test procedure (including electrical measurement at temperature and the relationship  
between the measured limits and those determined in the manufacturer's circuit simulations), design rules and process rules.  
Alternate measurement techniques, such as in-line monitors, are acceptable if properly documented. The following parameters  
are to be used as a guideline by the manufacturer's TRB in formulating the PM.  
a. General electrical parameters.  
(1) Sheet resistance: Structures should be included to measure the sheet resistance of all conducting layers.  
(2) Junction breakdown: Structures should be included to measure junction breakdown voltages for all diffusions.  
(3) Contact resistance: Structures should be included to measure contact resistance of all inter-level contacts.  
(3) Ionic contamination and minority carrier life time: Structures should be included to measure ionic contamination,  
such as sodium, in the gate, field, and inter-metal dielectrics and minority carrier lifetime.  
b. MOS parameters.  
(1) Gate oxide thickness: Structures should be included to measure gate oxide thickness for both “N” and “P” gate  
oxides as applicable.  
(2) MOS transistor parameters: A minimum set of test transistors should be included for the measurement of  
transistor parameters. The minimum transistor set should include a large geometry transistor of sufficient size  
that short channel and narrow width effects are negligible, and transistors that can separately demonstrate the  
maximum short channel effects and narrow width effects allowed by the geometric design rules. Both "N" and "P"  
transistors should be included for a complementary metal oxide semiconductor (CMOS) technology. If there is  
more than one nominal threshold voltage for either the "N" or "P" transistor type the minimum set should be  
included for each threshold. The transistor parameters to be measured are given below:  
(a) Threshold voltage: The linear threshold voltage (VT) for each transistor in the minimum set of transistors  
should be measured.  
(b) Linear transconductance: The linear transconductance (gm) for the full minimum set of transistors should be  
measured.  
(c) Effective channel length: The effective channel length for the minimum channel length of each transistor  
type should be measured.  
(d) Ion: Ion for representative transistors in the set.  
(e) Ioff: Ioff for representative transistors in the set.  
(f) Propagation delay: A test structure should be available in the form of a functional circuit from which  
propagation delay information can be measured at room temperature.  
(g) Field leakage: Field transistor leakage for the minimum spaced adjacent transistors at the maximum  
allowed voltage should be measured.  
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