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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX H  
H.3.2.1.5 Assembly and packaging. The manufacturer shall demonstrate the quality system and controls, including SPC  
and in-process monitoring programs for both in-house assembly line and any/all of their subcontractors performing assembly  
processing for SMD products.  
H.3.2.1.5.1 Assembly and packaging technology certification. As part of the certification, the manufacturer should identify  
the specific assembly technologies that are expected to be listed as part of the technology flow for QML and used in QML  
microcircuits. Those processes shall be qualified by addressing, as a minimum, the test in tables H-IA or H-IB as appropriate.  
An assembly technology consists of the materials and processes used for wafer saw, die attach, wire bond, flip chip  
attachment, package sealing, lead attach, solder dipping, marking, and any other process involved with the construction of the  
product. All supporting documentation and data shall be made available to the qualifying activity before or during the  
management and technology validation (see G.3.2.2.1).  
The following items shall be used as minimum requirements by the manufacturer and the QA in evaluating assembly and  
packaging for class level S product:  
a. Assembly processes.  
(1) Die attach.  
(2) Wire bond/bump.  
(3) Encapsulation.  
(4) Process monitors/SPC.  
(5) Inspections.  
(6) Tests – Mechanical, thermal, optical.  
(7) Lead or column attach.  
(8) Incoming tests or review of accompanying C of C on materials (e. package, die attach material, etc.).  
b. Package processes and technology.  
(1) Design.  
(2) Materials selection.  
(3) Assembly under supplier control.  
(a) By supplier.  
(b) Subcontracted.  
(4) Thermal characterization.  
(a) Hot spots.  
(b) Thermal impedance.  
(5) Electrical characterization.  
(a) At specification levels including voltage, full temperature range, and other excitation conditions.  
(b) Beyond specification conditions to determine margin.  
(c) Plan to address unspecified or untested parameters (Review analysis to ensure critical untested parameters  
are specified or addressed)  
(6) Package qualification data.  
(a) Incoming package tests on bare package.  
(b) Incoming tests on raw materials (e. die attach, etc.)  
(c) Mechanical tests.  
(d) Thermal tests.  
(e) Electrical tests.  
(f) Thermal impedance.  
(7) Column attachment.  
(a) ESD controls.  
(b) at 25°C electrical validation pre and post column attach.  
(c) Mechanical integrity.  
(d) Co-planarity.  
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