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5962-0422102QZA 参数 Datasheet PDF下载

5962-0422102QZA图片预览
型号: 5962-0422102QZA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 32256-Cell, CMOS, CBGA624,]
分类和应用: 可编程逻辑
文件页数/大小: 52 页 / 373 K
品牌: ACTEL [ Actel Corporation ]
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g. Devices built with case outlines Z, T, and N are equivalent to the same device built with case outline Y and M plus the  
solder column attachment. All required screening for devices built with case outline Z, T, and N are processed prior to  
the solder column attachment (same as case outline Y and M). After solder column attachment, Group A subgroups 1  
and 7 shall be performed to verify device functionality.  
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in  
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups  
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). Qualification inspection for all devices (01 to 08) complies with class Q  
level requirements only.  
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with  
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified. Quality conformance inspection for device  
class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for  
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections  
(see 4.4.1 through 4.4.4). Conformance inspection for devices 03, 04, 07, and 08 comply with class Q level requirement only,  
wafer lot specific group C inspection may be conducted under contract with acquiring activities.  
4.4.1 Group A inspection.  
a. Tests shall be as specified in table IIA herein.  
b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.  
c. Subgroup 4 (C and C  
IN OUT  
measurements) shall be measured only for initial qualification and after any process or  
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated  
terminal and GND at a frequency equal or less than 1 MHz. Sample size is on a minimum of three devices with no  
failures on a minimum of five worst case pins from each device.  
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may  
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document  
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity  
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device  
manufacturer's technical review board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the  
preparing activity or acquiring activity upon request. Testing shall be on all pins, on a minimum of three devices with  
zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD78  
may be used for reference.  
e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the  
functionality of the device. For device classes Q and V, subgroups 7, 8A, and 8B shall include verifying the  
functionality of the device.  
f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the requirements  
of group A, subgroups 1 and 7. The programming procedure used and the data generated shall be maintained by the  
device manufacturer and shall be made available to the preparing or acquiring activities.  
Note: The following steps are done prior to burn-in screening.  
(1) Programming requirements shall be based on wafer lot and the Enhanced Lot Acceptance (ELA) design shall be  
used. Sample size shall achieve 14 programmed devices with the maximum of five allowable programming failures  
19(5). In the occurrence of six or more programming failures, the wafer lot shall be put on hold until its  
programmability can be resolved, otherwise, the wafer lot shall be designated to be programmed by manufacturer  
only and be delivered to acquiring activities accepting lower programming yield.  
Note: Programming reliability is determined by programming algorithm (see 4.6 below), all parts passed programming  
shall be considered as reliable since it is verified with ELA; and programming yield shall not be used as a reliability  
indicator. Field programming yield can not be guaranteed, and manufacturer will replace all field programming rejects  
when the provided manufacturer's programming procedure is followed.  
(2) Retesting of devices due to failure shall be in accordance with the manufacture’s Quality Control Monitor (QCMON)  
for the purpose of determining the failure as True or False as defined in the QCMON.  
SIZE  
STANDARD  
5962-04221  
A
MICROCIRCUIT DRAWING  
DEFENSE SUPPLY CENTER COLUMBUS  
COLUMBUS, OHIO 43218-3990  
REVISION LEVEL  
SHEET  
C
9
DSCC FORM 2234  
APR 97  
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