1.6.4 Multi-Standard I/Os are available on all I/O pins. Below table shows all supported I/O standards.
Input/Output Supply Input Reference Board Termination
I/O Standard
Voltage (VCCI
)
Voltage (VREF
N/A
)
Voltage (VTT
N/A
)
LVTTL
3.3
2.5
1.8
1.5
3.3
3.3
1.5
3.3
2.5
2.5
3.3
LVCMOS 2.5V
LVCMOS 1.8V
LVCMOS 1.5V
3.3V PCI
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GTL+ 3.3V
1.0
1.2
HSTL Class I
SSTL3 Class I and II
SSTL2 Class I and II
LVDS
0.75
1.5
0.75
1.5
1.25
N/A
1.25
N/A
LVPECL
N/A
N/A
Each I/O provides programmable slew rates, drive strength, and weak pull-up and pull-down circuits (in the order of 10k), it
also includes three registers (input (InReg), output (OutReg), and enable (EnReg)). I/Os are organized into eight banks (0-7)
with two banks per device side. Each I/O bank has a common VCCI and a common reference-voltage bus. For each I/O bank,
multiple I/O standards may be selected, however, all I/O standards used in the same I/O bank shall have the same VCCI value
and the same VREF value (when required). VREF pin is not pre-defined; any user I/O in the bank can be selected to be a VREF
.
1.6.5 Routing Resource provides hierarchical routing structure that ties the logic modules, the embedded memory block, and
the I/O modules together. User designs can be implemented with manufacturer’s Designer software (see 6.7 herein), which
includes a Timer that supports timing-driven place-and-route; plus SmartPower for power estimation; PinEditor and I/O Attribute
Editor for I/O assignments and I/O attributes; Netlist Viewer and ChipPlanner for design implementation. Additionally, Libero
IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single
environment (see 6.7 herein).
1.6.6 Calculation for Junction Temperature. The temperature variable in the manufacturer’s Designer software refers to the
junction temperature, not the ambient, case, or board temperature. The operating temperature at case (T ) can be calculated
C
with JC = (T – T ) P; and the operating temperature at board interface (T ) for case outline Z can be calculated with JB
=
J
C
B
(T – T ) P. P is the device power consumption, which differs among user designs. Power usage can be determined by logic
J
B
cell utilization; clock usage and frequency; input cell utilization and frequency; output cell utilization, V
level and output
CCI
frequency; and static power consumption. The manufacturer’s software tool will assist users on power estimation.
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization Document
Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
SIZE
STANDARD
5962-04221
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
C
5
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
