AD9512
POWER
Table 9.
Parameter
Min Typ Max Unit Test Conditions/Comments
POWER-UP DEFAULT MODE POWER DISSIPATION
550 600
mW
Power-up default state; does not include power
dissipated in output load resistors. No clock.
POWER DISSIPATION
800
mW
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 62 MHz (5 pF load). Does not include
power dissipated in external resistors.
850
mW
mW
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 125 MHz (5 pF load). Does not include
power dissipated in external resistors.
Maximum sleep is entered by setting 0Ah<1:0> = 01b
and 58h<4> = 1b. This powers off all band gap
references. Does not include power dissipated in
terminations.
Set FUNCTION pin for PDB operation by setting
58h<6:5> = 11b. Pull PDB low. Does not include
power dissipated in terminations.
Full Sleep Power-Down
Power-Down (PDB)
35
60
60
80
mW
POWER DELTA
CLK1, CLK2 Power-Down
Divider, DIV 2 − 32 to Bypass
LVPECL Output Power-Down (PD2, PD3)
10
23
50
15
27
65
25
33
75
mW
mW
mW
For each divider.
For each output. Does not include dissipation
in termination (PD2 only).
LVDS Output Power-Down
CMOS Output Power-Down (Static)
CMOS Output Power-Down (Dynamic)
80
56
115
92
70
110
85
mW
mW
mW
For each output.
For each output. Static (no clock).
For each CMOS output, single-ended. Clocking at
62 MHz with 5 pF load.
150 190
CMOS Output Power-Down (Dynamic)
Delay Block Bypass
125
20
165 210
mW
mW
For each CMOS output, single-ended. Clocking at
125 MHz with 5 pF load.
Vs. delay block operation at 1 ns fs with maximum
delay; output clocking at 25 MHz.
24
60
Rev. A | Page 14 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
