AD9512
Parameter
DELAY BLOCK ADDITIVE TIME JITTER1
Min Typ Max
Unit
Test Conditions/Comments
Incremental additive jitter1
100 MHz Output
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100
0.61
0.73
0.71
1.2
0.86
1.8
1.2
2.1
1.3
2.7
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
2.0
2.8
1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CSB, SCLK (INPUTS)
CSB and SCLK have 30 kΩ
internal pull-down resistors
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
2.0
V
V
ꢀA
ꢀA
pF
0.8
1
110
2
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
2.0
2.7
V
V
nA
nA
pF
0.8
10
10
2
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK
Pulse Width High, tPWH
Pulse Width Low, tPWL
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
V
V
0.4
25
)
MHz
ns
ns
ns
ns
16
16
2
1
SCLK to Valid SDIO and SDO, tDV
CSB to SCLK Setup and Hold, tS, tH
CSB Minimum Pulse Width High, tPWH
6
2
3
ns
ns
ns
Rev. A | Page 12 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
