AD9512
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
Min Typ Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
40
fs rms
BW = 12 kHz − 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT2) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
55
fs rms
fs rms
BW = 12 kHz − 20 MHz (OC-3)
CLK1 = 400 MHz
215
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
222
225
225
fs rms
fs rms
fs rms
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz
Both LVDS (OUT3, OUT4) = 100 MHz
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both LVDS (OUT3, OUT4) = 50 MHz
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On)
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
264
319
395
fs rms
fs rms
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
LVDS (OUT4) = 50 MHz
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
Rev. A | Page 10 of 48
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