AD9512
Parameter
Min Typ Max
Unit
Test Conditions/Comments
CLK1 = 400 MHz
395
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
LVDS (OUT3) = 50 MHz
All LVPECL = 50 MHz
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
367
367
548
548
fs rms
fs rms
fs rms
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs Off)
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs Off)
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs On)
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs On)
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
CMOS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
275
400
fs rms
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Both CMOS (OUT3, OUT4) = 100 MHz (B Output On)
Divide Ratio = 4
CLK1 = 400 MHz
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
LVDS (OUT4) = 50 MHz
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
374
555
fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
CMOS (OUT4) = 50 MHz (B Output Off)
CLK1 = 400 MHz
Interferer(s)
Interferer(s)
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
CMOS (OUT4) = 50 MHz (B Output On)
Interferer(s)
Interferer(s)
Rev. A | Page 11 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
