W89C840F
TRDYB
IO/STS
Target Ready:
Asserted by the current target to indicate ability to
complete data transfer at the current data phase. When
W89C840F is operating at the bus slave mode, it asserts
TRDYB to indicate that the valid read data presents on
the bus or to indicate it is ready to accept data. Wait
states will be inserted if TRDYB deasserted. Data is
transferred at the rising edge of the PCI clock when
IRDYB and TRDYB are both asserted at the same time.
STOPB
IDSEL
IO/STS
I
PCI Stop:
Asserted by the current target to request master to stop
the current transaction.
PCI Initialization Device Select:
Asserted by host to signal the configuration access
request to W89C840F.
DEVSELB
IO/STS
PCI Device Select:
Asserted by the current target to indicate that it has
decoded its address as the current access target. When
W89C840F is the current master, it checks if the target
asserted this signal within 5 PCI clocks. If not,
W89C840F will abort the access operation. When
W89C840F is the target, it asserts DEVSELB in a
medium speed, i.e., within 2 clocks.
REQB
GNTB
O/TS
I/TS
PCI Request:
Asserted by W89C840F to request bus ownership.
REQB will be tri-stated when RSTB asserted.
PCI Grant:
Asserted by host to grant that W89C840F have got the
bus ownership. When RSTB asserted, W89C840F will
ignore GNTB.
PERRB
IO/STS
PCI Parity Error:
Asserted by the current data receiptor. When
W89C840F is the bus master, if a data parity error is
detected and the parity error response bit (FCS<6>) is
also set, it will set both bits of FCS<24> and C14<13>
as 1 to terminate the current transaction after the
current data phase is finished. When W89C840F is the
target, a data parity error is detected and the bit FCS<6>
is set, it will assert PERRB.
Publication Release Date:April 1997
- 7 -
Revision A1
ETC [ ETC ]
