FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols.
The LCD bias may be compensated for temperature using the LCD_DAC bits in I/O RAM. The bias may
be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and brownout modes, VBAT
in LCD mode). When the LCD_DAC bits are set to 000, the DAC is bypassed and powered down. This
can be used to reduce current in LCD mode.
Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is
controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers.
LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. The most sig-
nificant bit corresponds to COM3, the least significant to COM0.
1.5.13 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversion is available at RAM address 0x07. BME is ignored and assumed zero when system
power is not available.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
Battery measurement is not very linear but is very reproducible if properly calibrated. The best way to
perform the calibration is to set the battery input to the desired failure voltage and then have the MPU
firmware record that measurement. After this, the battery measurement logic may use the recorded value
as the battery failure limit. The same value can also be a calibration offset for any battery voltage display.
See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
1.5.14 EEPROM Interface
The 71M6531D/F and 71M6532D/F provide hardware support for either a two-pin or a three-wire (µ-wire)
type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is mul-
tiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX = 01. The MPU
communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to
write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to
EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also as-
serted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged
the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission and then holds in a high state until the next transmission. The EECTRL bits when the two-
pin interface is selected are shown in Table 43.
Table 43: EECTRL Bits for 2-pin Interface
Status
Bit
Read/ Reset
Write State
Name
Polarity Description
7
6
5
4
ERROR
BUSY
R
R
R
R
0
0
1
1
Positive 1 when an illegal command is received.
Positive 1 when serial data bus is busy.
RX_ACK
TX_ACK
Negative 0 indicates that the EEPROM sent an ACK bit.
Negative 0 indicates when an ACK bit has been sent to the
EEPROM.
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