CY28409
Byte 0:Control Register 0 (continued)
Bit
@Pup
Name
Description
3
Externally PCI_STP#
Selected
PCI_STP# reflects the current value of the external PCI_STP# pin.
0 = PCI_STP# pin is LOW.
2
1
0
Externally CPU_STP#
Selected
CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is LOW.
Externally FS_B
Selected
FS_B reflects the value of the FS_B pin sampled on power-up.
Externally FS_A
Selected
FS_A reflects the value of the FS_A pin sampled on power-up.
Byte 1: Control Register 1
Bit
@Pup
Name
SRCT, SRCC
Description
7
0
Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRCT, SRCC
Reserved
SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Reserved, Set = 1
Reserved
Reserved, Set = 1
Reserved
Reserved, Set = 1
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRCT, SRCC
SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 22, 2006
Page 5 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
