CY28409
Table 1. Frequency Select Table (FS_A, FS_B)
FS_A
FS_B
0
CPU
100 MHz
REF/N
SRC
3V66
66 MHz
REF/N
66 MHz
66 MHz
Hi-Z
PCIF/PCI
33 MHz
REF/N
33 MHz
33 MHz
Hi-Z
REF0
14.3 MHz
REF/N
REF1
14.31 MHz
REF/N
USB/DOT
48 MHz
REF/N
48 MHz
48 MHz
Hi-Z
0
0
0
1
1
100/200 MHz
REF/N
MID
1
200 MHz
133 MHz
Hi-Z
100/200 MHz
100/200 MHz
Hi-Z
14.3 MHz
14.3 MHz
Hi-Z
14.31 MHz
14.31 MHz
Hi-Z
0
MID
Table 2. Frequency Select Table (FS_A, FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
33 MHz
33 MHz
33 MHz
REF0
REF1
USB/DOT
48 MHz
48 MHz
48 MHz
0
0
1
0
1
0
200 MHz
400 MHz
266 MHz
100/200 MHz
100/200 MHz
100/200 MHz
66 MHz
66 MHz
66 MHz
14.3 MHz
14.3 MHz
14.3 MHz
14.31 MHz
14.31 MHz
14.31 MHz
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B except MID, VTT_PWRGD# employs a
Data Protocol
one-shot functionality in that once
a valid LOW on
VTT_PWRGD# has been sampled LOW, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
the case where FS_B is at mid level when VTT_PWRGD# is
sampled LOW, the clock chip will assume “Test Clock Mode.”
Once “Test Clock Mode” has been invoked, all further FS_B
transitions will be ignored and FS_A will asynchronously
select between the Hi-Z and REF/N mode. Exiting test mode
is accomplished by cycling power with FS_B in a HIGH or
LOW state.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
Serial Data Interface
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
11:18
Command Code – 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
Rev 1.0,November 22, 2006
Page 3 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
