CY28409
Byte 6: Control Register 6
Bit
7
@Pup
Name
Description
0
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
6
5
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
3
2
0
0
Reserved
Reserved, Set = 0
PCIF
PCI
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
1
0
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit @Pup
Name
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Table 6. Crystal Recommendations
Frequency
(Fund)
Drive
(max.)
ShuntCap Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
Cut
Loading Load Cap
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1. Crystal Capacitive Clarification
Rev 1.0,November 22, 2006
Page 7 of 16