CY28405
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
30:37
38
39
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
Test Bit 3
I2C_BYPASS_EN
Reserved, Set= 0 IO PLL TEST
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1= Force All PCI and PCIF Outputs to High Drive Strength
5
4
3
2
1
0
0
Reserved
FS_E
Reserved, Set= 0 PLL CPU VCO process correction test bit
Power up latched value of FS_E pin
HW
HW
HW
HW
HW
FS_D
Power up latched value of FS_D pin
FS_C
Power up latched value of FS_C pin
FS_B
Power up latched value of FS_B pin
FS_A
Power up latched value of FS_A pin
Byte 1: Control Register 1
Bit
7
@Pup
Name
Description
Reserved, set = 0
0
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
6
Reserved, set = 1
5
Reserved, set = 1
4
Reserved, set = 1
3
Reserved, set = 1
2
CPUT_ITP, CPUC_ITP
CPUT/C_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
1
0
1
1
CPUT1, CPUC1
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPUT0, CPUC0
CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Rev 1.0,November 20, 2006
Page 5 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
