CY28405
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
1
DOT_48
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
Reserved
Reserved
HW
3V66_3/VCH/SELVCH
3V66_3/VCH/SELVCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
May be written to override the power-up value.
4
1
3V66_3/VCH/SELVCH
3V66_3/VCH/SELVCH Output Enable
0 = Disabled,1 = Enabled
3
2
1
1
Reserved
3V66_2
Reserved
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
0
1
1
3V66_1
3V66_0
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF
PCIF
Test Clock Mode
0 = Disabled, 1 = Enabled
PCI
3V66
When Test Clock Mode is enabled, the FS_A/REF_0 pin reverts to a
dedicated FS_A input, allowing asynchronous selection between Hi-Z and
REF/N mode.
3V66_3/VCH/SELVCH
USB_48
DOT_48
CPUT, CPUT_ITP
CPUC,CPUC_ITP
6
5
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
3
2
0
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
PCIF
PCI
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
3V66
CPUT,CPUT_ITP
CPUC,CPUC_ITP
1
0
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit @Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
7
6
5
4
3
2
1
0
1
0
0
1
0
0
Vendor ID Bit 2
Vendor ID Bit 1
Rev 1.0,November 20, 2006
Page 7 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
