CY28372
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Bit
28
29
Description
Acknowledge from slave
Stop
Bit
21:27
28
Slave address – 7 bits
Read = 1
29
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
30:37
38
39
Device Configuration Map
Data Bytes 0 to 3: Reserved for ZDB Registers
Byte 4
Bit
@Pup
Name
Description
[7..4]
CPU
ZCLK
AGPPCI
Bit 7
1
Frequency Select Register
(FS3)
Bit2 = 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
133.3
133.3
133.3
133.3
133.3
133.3
133.3
133.3
100.0
100.0
100.0
100.0
100.0
100.0
111.0
111.0
66.7
66.7
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
55.533.3
66.733.3
50.033.3
66.733.3
50.033.3
66.733.3
50.033.3
66.633.3
55.533.3
Bit 6
Bit 5
Bit 4
0
0
0
Frequency Select Register
(FS2)
100.0
100.0
133.3
133.3
166.6
166.6
66.7
Frequency Select Register
(FS1)
Frequency Select Register
(FS0)
66.7
100.0
100.0
133.3
133.3
166.5
166.5
Bit2 = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
114.5
120.0
133.3
133.3
133.3
145.7
150.0
166.6
111.1
137.4
144.9
150.0
155.1
166.6
180.1
200.0
95.4
100.0
83.3
63.631.8
66.733.3
66.733.3
74.133.3
83.333.3
64.832.4
66.733.3
66.733.3
66.733.3
68.734.4
64.432.2
66.733.3
68.934.5
66.733.3
67.633.8
66.733.3
111.1
133.3
116.6
100.0
111.1
133.3
137.4
144.9
150.0
124.1
133.3
135.1
133.3
Bit 3
0
FS_Override
Frequency Selection Source:
0 = Select through hardware strapping, latched inputs
1 = Select through I2C
Bit 2
Bit 1
Bit 0
0
1
0
Frequency Select Register Most significant bit of I2C Frequency Select Register
Spread Spectrum Control
Output Disable
0 = Normal, 1 = Spread Spectrum enable
0 = Normal, 1 = three-state all outputs
Byte 5
Bit
@Pup
Name
Reserved
Description
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev 1.0,November 20, 2006
Page 5 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
