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CY28372OXCT 参数 Datasheet PDF下载

CY28372OXCT图片预览
型号: CY28372OXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 矽统746的AMD Athlon ™ / AMD的Duron ™时钟合成器 [SiS 746 AMD Athlon⑩/AMD Duron⑩ Clock Synthesizer]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 17 页 / 227 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28372  
Byte 12  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
@Pup  
Name  
Description  
REF_2 Output Control (default: off)  
0
0
0
0
0
0
REF_2  
Reserved  
Reserved  
DARAG2  
DARAG1  
DARAG0  
Reserved  
Reserved  
Dial-a-Ratio¥ AGP[0:1].  
Programming these bits allow modifying the frequency ratio of the  
AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. (the ratio  
of AGP to PCI is retained at 2:1)  
DARAG[2:0]  
000  
VC0/AGP Ratio  
- (Frequency Selection Default)  
001  
010  
6
8
011  
100  
101  
110  
9
10  
12  
12  
12  
111  
Bit 1  
0
0
Fixed_PCI_SEL  
Fixed_3V66_SEL  
PCI output frequency select mode  
(valid only when Fixed_3V66_SEL = 1)  
0 = Use Frequency Selection Table settings  
1 = Use Fractional Aligner settings (default)  
Bit 0  
3V66 and PCI output frequency select mode  
0 = Use Frequency Selection Table settings (default)  
1 = Use Fractional Aligner settings  
Byte 13  
Bit  
@Pup  
Name  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
0
0
0
Reserved  
N6 (MSB)  
N5  
Reserved  
Dial-a-Frequency® Control Register N. These bits are for programming  
the PLL’s internal N register. This access allows the user to modify the  
CPU frequency with great accuracy. All other synchronous clocks (clocks  
that are generated from the same PLL, such as PCI, remain at their  
existing ratios relative to the CPU clock. (should be written together with  
Control Register R)  
N4  
N3  
N2  
N1  
N0 (LSB)  
Byte 14  
Bit  
@Pup  
Name  
Reserved  
R5 (MSB)  
R4  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
0
0
0
Reserved  
Dial-a-Frequency Control Register R  
These bits are for programming the PLL’s internal R register. This access  
allowsthe usertomodifytheCPU frequencywithgreat accuracy. Allother  
synchronous clocks (clocks that are generated from the same PLL, such  
as PCI, remain at their existing ratios relative to the CPU clock.  
(should be written together with Control Register N)  
R3  
R2  
R1  
R0 (LSB)  
R & N Select  
R and N register mux selection.  
0 = R and N values come from the ROM.  
1 = data is loaded from the DAF registers into R and N.  
Rev 1.0,November 20, 2006  
Page 8 of 17