CY28372
Table 1. Frequency Selection Table
Input Conditions
Output Frequency
VCO
Freq.
(MHz)
I2C Option
(byte 4, bit 2)
CPU
(MHz)
ZCLK
(MHz)
AGP
(MHz)
PCI
(MHz)
FS(3:0)
0
0
0
0
0
0
0
0
0000
0001
133.3
133.3
133.3
133.3
133.3
133.3
133.3
133.3
100.0
100.0
100.0
100.0
100.0
100.0
111.0
111.0
114.5
120.0
133.3
133.3
133.3
145.7
150.0
166.6
111.1
137.4
144.9
150.0
155.1
166.6
180.1
200.0
66.7
66.7
50.0
66.7
50.0
66.7
50.0
66.7
55.5
66.7
50.0
66.7
50.0
66.7
50.0
66.6
55.5
63.6
66.7
66.7
74.1
83.3
64.8
66.7
66.7
66.7
68.7
64.4
66.7
68.9
66.7
67.6
66.7
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.8
33.3
33.3
33.3
33.3
32.4
33.3
33.3
33.3
34.4
32.2
33.3
34.5
33.3
33.8
33.3
400.0
400.0
400.0
400.0
400.0
400.0
666.5
666.5
400.0
400.0
400.0
400.0
400.0
400.0
666.1
666.1
572.5
600.0
666.5
666.5
666.5
582.8
600.0
666.5
666.5
549.6
579.5
600.0
620.3
666.5
540.4
400.0
66.7
0010
100.0
100.0
133.3
133.3
166.6
166.6
66.7
0011
0100
0101
0110
0111
0
(default) 1000
1001
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
66.7
1010
100.0
100.0
133.3
133.3
166.5
166.5
95.4
1011
1100
1101
1110
1111
0000
0001
100.0
83.3
0010
0011
111.1
133.3
116.6
100.0
111.1
133.3
137.4
144.9
150.0
124.1
133.3
135.1
133.3
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
Rev 1.0,November 20, 2006
Page 3 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
