P4C1024L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
TRUTH TABLE
AC TEST CONDITIONS
Mode
Standby
Standby
CE1 CE2 OE WE I/O
Power
Standby
Standby
Input Pulse Levels
GND to 3.0V
H
X
X
X
High Z
High Z
High Z
X
L
X
X
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
L
H
H
H
Active
DOUT Disabled
See Fig. 1 and 2
DOUT
DIN
L
L
H
H
L
H
L
Read
Write
Active
Active
X
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Because of the high speed of the P4C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leadsthatcausesupplybouncemustbeavoidedbybringingtheVCC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground.
Document # SRAM125 REV C
Page 6 of 10
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
