PACE1750AE
1,2 (continued)
SIGNAL PROPAGATION DELAYS
20 MHz
30 MHz
40 MHz
Min
Max
25
26
26
35
35
35
50
40
Min
Max
Min
Max
Symbol
tFC(IBD)V
tC(SNW)
Parameter
Unit
IB0-IB15
SNEW
25
25
25
35
35
35
50
40
20
22
22
30
30
30
45
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRIGO RST
DMA enable
DMA enable
tFC(TGO)
tRSTL(DMA ENL)
tC(DME)
Normal power up
tFC(NPU)
tC(ER)
Clock to major error unrecoverable
RESET
tRSTL(NPU)
tREQV(C)
tC(REQ)X
tFV(BB)H
tBBH(F)X
tIRV(C)
Console request
0
10
5
0
10
5
0
10
5
Console request
Level sensitive faults
Level sensitive faults
IOL1-2INT user interrupt (0-5) setup
5
5
5
0
0
0
Power down interrupt level sensitive
hold
tC(IR)X
10
20
10
20
10
15
ns
Reset pulse width
ns
ns
ns
ns
t
RSTL (tRSTH)
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
17
5
17
5
13
5
tC(XX)Z
5
5
5
tf(F), t1(1)
tr, tf
Notes
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in
parenthesesindicates"to"signal. WhentheCPUclockisoneofthesignalelements, eithertherisingedge"C"orthefallingedge"FC"isreferenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Do c um e nt # MICRO-2 REV G
Pa g e 6 o f 25
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
