PACE1750AE
DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE
ThePACE1750AEachievesa41%boostinperformance(inclockcycles)overthePACE1750A. Thisreductioninclocks
per instruction is because of three architectural enhancements:
1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU’s
peripheral chips).
3) Branch calculation logic.
The table below shows how the MAC improves all multiply operations — both integer and floating point — by 477% to
760%.
PACE1750AE
PACE1750A
Instruction
Integer Add/Sub
Clocks
Execution
Clocks
Execution
Time (40 MHz) #Clocks (%)
Gain
Time (40 MHz)
100ns
150ns
4
6
4
9
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
—
50
Double Precision Integer Add/Sub
Integer Multiply
4
100ns
225ns
23
69
28
51
43
96
12
4
575
760
55
Double Precision Integer Add/Sub
Floating Add/Sub
9
18
34
9
450ns
850ns
Extended Floating Add/Sub
Floating Multiply
50
225ns
425ns
200ns
100ns
675ns
477
564
50
Extended Floating Point Multiply
Branch (Taken)
17
8
Branch (Not Taken)
4
—
Flt’g’ Point Polynomial Step (Mul+Add/Sub)
Ext Flt’g’ Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
27
51
—
71
147
—
263
2400
41/59
1275ns
3.56
PACE1750AE BUILT IN FUNCTIONS
AcoresetofadditionalinstructionshavebeenincludedinthePACE1750AE. TheseinstructionsutilizetheBuiltlnFunction
(BlF)opcodespace. TheobjectiveofthesenewopcodesistoenhancetheperformanceofthePACEincriticalapplication
areassuchasnavigation, DSP, transcendentalsandotherLINPAKandmatrixtypeinstructions. BelowisalistoftheBlFs
and their execution times (N = the number of elements in the vector being processed).
Address
Mode
Number of
Clocks
Instruction
Memory Parametric Dot Product—Single
Memory Parametric Dot Product—Double
3 x 3 Register Dot Product
Double Precision Multiply Accumulate
Polynomial
Mnemonic
VDPS
VDPD
R3DP
MACD
POLY
CLAC
STA
Notes
4F3(RA)
4F1(RA)
4F03
10 + 8 • N
Interruptable
Interruptable
10+16 • N
6
4F02
8
4F06
7 • N - 2
Clear Accumulator
4F00
4
Store Accumulator (32-Bit)
Store Accumulator (48-Bit)
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
4F08
7
STAL
4F04
11
LAC
4F05
9
LACL
4F07
9
MMPG
LTAR
LTBR
4F0F
4F0D
4F0E
16+8 • N
Privileged
Load Timer A Reset Register
Load Timer B Reset Register
4
4
Do c um e nt # MICRO-2 REV G
Pa g e 2 o f 25
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
