April 2007
rev 1.2
ASM2I9940L
ASM2I9940L
Z0=50Ω
Z0=50Ω
Pulse
Generator
Z=50Ω
RT=50Ω
VTT
Figure 1. LVCMOS_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
ASM2I9940L
Z0=50Ω
Z0=50Ω
Differential
Pulse Generator
Z=50Ω
RT = 50Ω
RT=50Ω
VTT
Figure 2. PECL_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
VC
VCC ÷2
GND
PECL_CLK
PECL_CLK
LVCMOS_CLK
VCMR
VPP
VCC
VC
Q
VCC ÷2
V
CC ÷2
GND
GND
Q
tPD
tPD
Figure 4. LVCMOS Propagation Delay (tPD
) Test Reference
Figure 3. Propagation Delay (tPD
) Test Reference
VCC
VCC ÷2
GND
VCC
V
CC ÷2
GND
tP
VOH
VCC ÷2
GND
T0
tSK(O)
DC (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 5. Output Duty Cycle (DC)
Figure 6. Output–to–Output Skew tSK(O)
VCC = 3.3V VCC = 2.5V
VCC = 3.3V VCC = 2.5V
2.4
1.8V
0.6V
2.0
0.8
1.7V
0.7V
0.55
tR
tR
tF
tF
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
7 of 13
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
