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ASM2P9940LG-32-LR 参数 Datasheet PDF下载

ASM2P9940LG-32-LR图片预览
型号: ASM2P9940LG-32-LR
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压1:18时钟分配芯片 [Low Voltage 1:18 Clock Distribution Chip]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 13 页 / 485 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第1页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第2页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第3页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第4页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第6页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第7页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第8页浏览型号ASM2P9940LG-32-LR的Datasheet PDF文件第9页  
April 2007  
rev 1.2  
ASM2I9940L  
Table 7. DC Characteristics (TA = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5%)  
Symbol  
Characteristic  
Min  
Typ  
Max  
Unit  
Condition  
VIH  
Input HIGH Voltage  
CMOS_CLK  
CMOS_CLK  
PECL_CLK  
PECL_CLK  
2.0  
VCCI  
V
VIL  
Input LOW Voltage  
Peak–to–Peak Input  
Voltage  
0.8  
V
VPP  
500  
1000  
mV  
VCMR  
VOH  
VOL  
IIN  
Common Mode Range  
Output HIGH Voltage  
Output LOW Voltage  
Input Current  
VCC-1.4  
1.8  
VCC-0.6  
V
V
IOH = -20mA  
IOH = 20mA  
0.5  
V
±200  
µA  
pF  
pF  
CIN  
Input Capacitance  
4.0  
10  
Cpd  
ZOUT  
Power Dissipation Capacitance  
Output Impedance  
per output  
23  
Maximum Quiescent Supply Current  
0.5  
1.0  
mA  
ICC  
Table 8. AC Characteristics (TA =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5%)  
Symbol  
Characteristic  
Min  
Typ  
Max  
Unit  
Condition  
Fmax  
Maximum Input Frequency  
250  
MHz  
PECL_CLK < 150MHz 2.0  
CMOS_CLK < 150MHz 1.7  
2.8  
2.5  
3.5  
3.0  
tPLH  
tPLH  
Propagation Delay  
nS  
nS  
Note1.  
PECL_CLK > 150MHz 2.0  
CMOS_CLK > 150MHz 1.8  
2.9  
2.5  
3.8  
3.3  
Propagation Delay  
PECL_CLK  
CMOS_CLK  
150  
150  
tsk(o)  
Output-to-output Skew  
pS  
nS  
Note1  
PECL_CLK < 150MHz  
CMOS_CLK < 150MHz  
1.5  
1.3  
tsk(pp)  
tsk(pp)  
Part–to–Part Skew  
Part–to–Part Skew  
Notes1,2  
PECL_CLK > 150MHz  
CMOS_CLK > 150MHz  
1.8  
1.5  
nS  
pS  
Notes1,2  
Notes1,3  
850  
tsk(pp)  
DC  
Part–to–Part Skew  
Output Duty Cycle  
Output Rise/Fall Time  
PECL_CLK CMOS_CLK  
750  
fCLK < 134 MHz  
fCLK <250 MHz  
45  
40  
50  
50  
55  
60  
%
%
Input DC = 50%  
Input DC = 50%  
tr, tf  
0.3  
1.2  
nS  
0.5 - 1.8 V  
Note: 1.Tested using standard input levels, Production tested @ 150MHz.  
2. Across temperature and voltage ranges, includes output skew.  
3. For a specific temperature and voltage, includes output skew.  
Low Voltage 1:18 Clock Distribution Chip  
5 of 13  
Notice: The information in this document is subject to change without notice.