April 2007
rev 1.2
ASM2I9940L
Table 9. DC Characteristics (TA = -40° to +85°C, VCCI = 2.5V ± 5%, VCCO = 2.5V ± 5%)
Symbol
VIH
Characteristic
Min
2.0
Typ
Max
VCCI
0.8
Unit
V
Condition
Input HIGH Voltage
CMOS_CLK
VIL
Input LOW Voltage
CMOS_CLK
V
Peak–to–Peak Input
VPP
PECL_CLK
PECL_CLK
500
1000
mV
Voltage
VCMR
Common Mode Range
VCC-1.0
1.8
VCC-0.6
V
V
VOH
VOL
IIN
Output HIGH Voltage
Output LOW Voltage
Input Current
IOH = -20mA
IOH = 20mA
0.5
±200
V
µA
pF
pF
ꢀ
CIN
Input Capacitance
4.0
10
Cpd
ZOUT
Power Dissipation Capacitance
Output Impedance
per output
18
23
28
Maximum Quiescent Supply Current
0.5
1.0
mA
ICC
Table 10. AC Characteristics (TA =-40° to +85°C, VCCI = 2.5V ± 5%, VCCO = 2.5V ± 5%)
Symbol
Characteristic
Min Typ Max Unit
Condition
Fmax
Maximum Input Frequency
200
MHz
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
2.6
2.3
4.0
3.1
5.2
tPLH
tPLH
Propagation Delay
Propagation Delay
nS
nS
pS
nS
nS
nS
Note1.
4.0
PECL_CLK > 150MHz
2.8
3.8
5.0
4.0
CMOS_CLK > 150MHz
2.3
3.1
Output-to-output Skew
Within one bank
PECL_CLK
CMOS_CLK
200
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
Note1.
Notes1,2
Notes1,2
Notes1,3
200
2.6
1.7
PECL_CLK < 150MHz
Part–to–Part Skew
Part–to–Part Skew
Part–to–Part Skew
CMOS_CLK < 150MHz
2.2
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
1.7
1.2
1.0
PECL_CLK
CMOS_CLK
45
40
0.3
50
50
55
%
%
nS
Input DC = 50%
Input DC = 50%
fCLK < 134 MHz
DC
tr, tf
Output Duty Cycle
60
f
CLK <250 MHz
Output Rise/Fall Time
1.2
0.5 - 1.8 V
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
6 of 13
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
