April 2007
rev 1.2
ASM2I9940L
Table 5. DC Characteristics (TA =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
CMOS_CLK
2.0
VCCI
V
VIL
Input LOW Voltage
CMOS_CLK
0.8
V
Peak–to–Peak Input
Voltage
VPP
PECL_CLK
PECL_CLK
500
1000
mV
VCMR
VOH
VOL
IIN
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
VCC-1.4
2.4
VCC-0.6
V
V
IOH = –20mA
IOH = 20mA
0.5
V
±200
µA
pF
pF
ꢀ
CIN
Input Capacitance
4.0
10
Cpd
ZOUT
ICC
Power Dissipation Capacitance
Output Impedance
per output
18
23
28
Maximum Quiescent Supply Current
0.5
1.0
mA
Table 6. AC Characteristics (TA = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ Max
Unit
Condition
Fmax
Maximum Input Frequency
250
MHz
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
2.0
1.7
2.7
2.5
3.4
3.0
tPLH
Propagation Delay
nS
Note1.
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
2.0
1.8
2.9
2.5
3.7
3.2
tPLH
tsk(o)
tsk(pp)
Propagation Delay
Output-to-output Skew
Part-to-Part Skew
nS
pS
nS
PECL_CLK
CMOS_CLK
150
150
Note1.
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
1.5
1.3
Notes1,2
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
1.8
1.5
850
750
tsk(pp)
tsk(pp)
Part-to-Part Skew
Part-to-Part Skew
nS
pS
Notes1,2
Notes1,3
PECL_CLK CMOS_CLK
fCLK < 134 MHz
fCLK <250 MHz
45
40
50
50
55
60
%
%
Input DC = 50%
Input DC = 50%
DC
tr, tf
Output Duty Cycle
Output Rise/Fall Time
0.3
1.1
nS
0.5 – 2.4 V
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
4 of 13
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
